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[ak4685] ms1106-e-00 2009/08 - 1 - general description the ak4685 is a single chip codec that integrates 4-channel adc, 2-channel dac and a stereo capacitor less headphone amplifier. the converters are designed with an e nhanced dual bit architecture for the adc, and an advanced multi-bit architecture for the dac?s, enabling very low noise performance and achieving wide dynamic range. t he differential analog inputs and output s cancel noise on analog signal lines. therefore, a stable system can be designed. the ak4685 has a dynamic r ange of 102db for adc, 106db for dac, and is well suited for di gital tv and home theater systems. features ? asynchronous adc/dac1/dac2 operation ? 4ch 24bit adc - differential input - 64x oversampling - sampling rate up to 48khz - linear phase digital anti-alias filter - s/(n+d): 90db - dynamic range, s/n: 102db - digital hpf for offset cancellation - channel independent digital vo lume (+24/-103db, 0.5db/step) - soft mute ? two 2ch 24bit dac?s - differential/single-end ouput (dac1) - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - s/(n+d): 92db - dynamic range, s/n: 106db - channel independent digital vo lume (+12/-115db, 0.5db/step) - soft mute ? 40mw capless stereo headphone amplifier - output power: 1.21vrms @ 3.3v, thd+n(min) = -40db - dynamic range, s/n: 96db - pop noise free at power-on/off and mute ? independent mute pins for 2 lines ? high jitter tolerance ? ttl level digital i/f ? external master clock input: 256fs, 384fs, 512fs 768fs (fs=32khz 48khz) 128fs, 192fs, 256fs 384fs (fs=64khz 96khz) 128fs, 192fs (fs=120khz ~ 192khz) ? audio serial i/f (porta/b/c) - master/slave mode (portb) - i/f format : msb justified, i 2 s ak4685 multi-channel codec with differential analog i/o
[ak4685] ms1106-e-00 2009/08 - 2 - ? i 2 c bus p i/f for mode setting ? operating voltage: - digital out: 3.0v 5.25v, - digital in: 4.75v 5.25v, - charge pump: 3.0v 3.6v, - analog: 4.75v ~ 5.25v ? package: 64pinlqfp (0.5mm pitch) a inl1- a inl1+ dacl+ dacl- dacr+ dacr- hpl hpr mcb/xti xto mcko bickb lrckb sdtob1 sdtob2 msb mclka bicka lrcka sdtia portb porta serial i/f 2ch dac serial i/f 2ch dac l1+ r1+ l2 r2 serial i/f mclkc bickc lrckc sdtic portc l1- r1- a inr1- a inr1+ - + - + charge pump a vdd1 vss6 a vdd2 vss3 a vdd3 vss5 vcom dvdd1 vss7 dvdd2 vss2 dvdd3 vss1 tvdd pdn a inl2- a inl2+ a inr2- a inr2+ - + - + pvdd pvss pvee cp cn hp amp hp amp diff/s.e. amp diff/s.e. amp x ?tal os cillato r sda scl mt1n mt2n sgl control i/f dvol dvol 4ch adc dvol lin1- lin1+ lampo1 lv com1 rin1- rin1+ rampo1 rvcom1 lin2- lin2+ lampo2 lv com2 rin2- rin2+ rampo2 rvcom2 ak4685 block diagram
[ak4685] ms1106-e-00 2009/08 - 3 - ordering guide ak4685eq -20 +85 c 64pin lqfp (0.5mm pitch) AKD4685 evaluation board for the ak4685 pin layout rvcom1 49 rin1+ 50 rampo1 51 lampo1 52 lin1- 53 lin1+ 54 lvcom1 55 lrckb 56 57 58 59 sdtob1 60 sdtob2 61 bickb 62 vss7 63 64 48 47 vss6 46 vcom 45 lvcom2 44 lin2+ 43 lin2- 42 lampo2 41 rampo2 40 rin2- 39 rin2+ 38 rvcom2 37 vss5 36 a vdd3 35 hpr 34 hpl 33 1 lrckc 2 msb 3 4 5 6 7 scl 8 sd a 9 dvdd3 10 vss1 11 sdtic 12 bickc 13 mt1n 14 mt2n 15 dvdd2 16 vss2 vss4 32 pvdd 31 cn 30 29 28 27 26 rout- 25 rout+ 24 vss3 23 a vdd2 22 sgl 21 lrcka 20 mclka 19 bicka 18 sdtia 17 a k4685eq top view pvee m cb/xti xto lout+ lout- nc cp tvdd mcko pdn mclkc dvdd1 avdd1 rin1-
[ak4685] ms1106-e-00 2009/08 - 4 - pin/function no. pin name i/o function 1 xto o x?tal output pin 2 mcb/xti i adc master clock input /x?tal input pin 3 msb i portb master mode select pin. ?l? (connected to the ground): slave mode. ?h? (connected to dvdd2): master mode. 4 lrckc i dac2 input channel clock pin 5 mclkc i dac2 master clock input pin 6 bickc i dac2 audio serial data clock pin 7 sdtic i dac2 audio serial data input pin 8 vss1 - dac2 digital ground pin, 0v 9 dvdd3 - dac2 digital power supply pin, 4.75v 5.25v 10 sda i/o control data input/output pin 11 scl i control data clock pin 12 pdn i power-down mode & reset pin when ?l?, the ak4685 is powered-down, all registers are reset. and then all digital output pins go ?l?. the ak4685 must be reset once upon power-up. 13 mt1n i dac1 mute pin ?h?: normal operation ?l?: mute 14 mt2n i dac2 mute pin ?h?: normal operation ?l?: mute 15 dvdd2 - dac1 digital power supply pin, 4.75v 5.25v 16 vss2 - dac1 digital ground pin, 0v 17 sdtia i dac1 audio serial data input pin 18 bicka i dac1 audio serial data clock pin 19 mclka i dac1 master clock input pin 20 lrcka i dac1 input channel clock pin 21 sgl i analog output mode select pin. ?l? (connected to the ground): differential mode. ?h? (connected to dvdd): single end mode. 22 avdd2 - dac1 analog power supply pin, 4.75v 5.25v 23 vss3 - dac1 analog ground pin, 0v 24 rout+ o rch positive analog output pin 25 rout- o rch negative analog output pin 26 lout+ o lch positive analog output pin 27 lout- o lch negative analog output pin 28 nc - no internal bonding. this pin must be connected to ground. 29 cp i positive charge pump capacitor terminal pin 30 cn i negative charge pump capacitor terminal pin 31 pvdd - charge pump power supply pin, 3.0v ~ 3.6v. 32 vss4 - charge pump ground pin, 0v. 33 pvee - charge pump negative power output pin. 34 hpl o lch headphone-amp output pin 35 hpr o rch headphone-amp output pin 36 avdd3 - dac2 analog power supply pin, 4.75v 5.25v 37 vss5 - dac2 analog ground pin, 0v 38 rvcom2 o rch vcom output 2 pin 39 rin2+ i rch positive analog input 2 pin 40 rin2- i rch negative analog input 2 pin 41 rampo2 o rch pre-amp output 2 pin 42 lampo2 o lch pre-amp output 2 pin
[ak4685] ms1106-e-00 2009/08 - 5 - 43 lin2- i lch negative analog input 2 pin 44 lin2+ i lch positive analog input 2 pin 45 lvcom2 o lch vcom output 2 pin 46 vcom - dac/adc common voltage out put pin. avdd1 x 0.5(typ). 10 f capacitor should be connected to vss6 externally. 47 vss6 - adc analog ground pin, 0v 48 avdd1 - adc analog power supply pin, 4.75v 5.25v 49 rvcom1 o rch vcom output 1 pin 50 rin1+ i rch positive analog input 1 pin 51 rin1- i rch negative analog input 1 pin 52 rampo1 o rch pre-amp output 1 pin 53 lampo1 o lch pre-amp output 1 pin 54 lin1- i lch negative analog input 1 pin 55 lin1+ i lch positive analog input 1 pin 56 lvcom1 o lch vcom output 1 pin 57 lrckb i/o adc channel clock pin 58 bickb i/o adc audio serial data clock pin 59 sdtob2 o adc audio serial data output 2 pin 60 sdtob1 o adc audio serial data output 1 pin 61 mcko o master clock output pin 62 tvdd - output buffer power supply pin, 3.0v 5.25v 63 vss7 - adc digital ground pin, 0v 64 dvdd1 - adc digital power supply pin, 4.75v 5.25v note 1. all digital input pins must not be left floating. note 2 . ac coupling capacitors should be connected to analog i nput pins (lin1+/-, lin 2+/-, rin1+/-, rin 2+/-). note 3. ac coupling capacitors should be connected to analog output pins (lout+/-, rout+/-). the unused i/o pins must be processed appropriately as below. classification pin name setting lout+/-, rout+/-, these pins should be open. lin1+, lin 2+, rin1+, rin 2+ these pins should be connected to each vcomo pins (lvcom1/2,rvcom1/2) analog lin1-, lin 2-, rin1-, rin 2- these pins should be connected to each ampo pins (lampo1/2,rampo1/2) sdtob1, sdtob2, xto, mclko, lrckb(master), bickb(master) these pins should be open. mclka/c, mcb, lrcka-c(slave), bicka-c(slave), sdtia,c, msb, mt1n, mt2n, sgl these pins should be connected to ground. digital sda, scl these pins should be pulled-up to dvdd3. - nc this pin should be connected to ground.
[ak4685] ms1106-e-00 2009/08 - 6 - power-down pin states no. pin name i/o power-down (pdn pin = ?l?) 1 xto o h (dvdd1) 2 mcb/xti i pull-down 25k ? (typ) to vss7 3 msb i hi-z 4 lrckc i hi-z 5 mclkc i hi-z 6 bickc i hi-z 7 sdtic i hi-z 8 vss1 - - 9 dvdd3 - - 10 sda i/o hi-z 11 scl i hi-z 12 pdn i - 13 mt1n i hi-z 14 mt2n i hi-z 15 dvdd2 - - 16 vss2 - - 17 sdtia i hi-z 18 bicka i hi-z 19 mclka i hi-z 20 lrcka i hi-z 21 sgl i hi-z 22 avdd2 - - 23 vss3 - - 24 lout+ o pull up 190k ? (typ) to avdd2 25 lout- o hi-z 26 rout+ o pull up 190k ? (typ) to avdd2 27 rout- o hi-z 28 nc - hi-z 29 cp i pull-up 80 ? (typ) to pvdd cn i pull-down 80 ? (typ) to vss4 31 pvdd - - 32 vss4 - - 33 pvee o pull-down 17.5k ? (typ) to vss4 34 hpl o pull-down 20 ? (typ) to vss5 35 hpr o pull-down 20 ? (typ) to vss5 36 avdd3 - - 37 vss5 - - 38 rvcom2 o hi-z 39 rin2+ i hi-z 40 rin2- i hi-z 41 rampo2 o hi-z 42 lampo2 o hi-z 43 lin2- i hi-z 44 lin2+ i hi-z 45 lvcom2 o hi-z 46 vcom - pull-down 500 ? (typ) to vss6 47 vss6 - - 48 avdd1 - - 49 rvcom1 o hi-z 50 rin1+ i hi-z
[ak4685] ms1106-e-00 2009/08 - 7 - no. pin name i/o power-down (pdn pin = ?l?) 51 rin1- i hi-z 52 rampo1 o hi-z 53 lampo1 o hi-z 54 lin1- i hi-z 55 lin1+ i hi-z 56 lvcom1 o hi-z 57 lrckb i/o hi-z (msb pin = ?l?) l (msb pin = ?h?) 58 bickb i/o hi-z (msb pin = ?l?) l (msb pin = ?h?) 59 sdtob2 o l 60 sdtob1 o l 61 mcko o l (x?tal mode) mcb through (external clk mode) 62 tvdd - - 63 vss7 - - 64 dvdd1 - - note 1. all digital input pins must not be left floating. note 4. the differential output pins of analog line-out (lout+ ? lout- and rout+ ? rout-) are connected internally via 150k ? (typ) resistors. note 5. preamplifier output pins (lampo1 ? lvcom1, rampo1 ? rvcom1, lampo2 ? lvcom2, rampo2 ? rvcom2) are connected internally via 200k ? (typ) resistors.
[ak4685] ms1106-e-00 2009/08 - 8 - absolute maximum ratings (vss1-7=0v; note 6 ) parameter symbol min max units power supply tvdd dvdd1 dvdd2 dvdd3 avdd1 avdd2 avdd3 pvdd -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 6.0 6.0 6.0 4.0 v v v v v v v v input current (any pins except for supplies) iin - 10 ma digital input voltage 1 (mcb/xti, msb pins) vind1 -0.3 dvdd1+0.3 v digital input voltage 2 (sdtia, bicka, mclka, lrcka and sgl pins) vind2 -0.3 dvdd2+0.3 v digital input voltage 3 ( lrckc, mclkc, bickc, sdti c, sda, scl, pdn, mt1n and mt2n pins ) vind3 -0.3 dvdd3+0.3 v digital input voltage 4 (lrckb, bickb pins) vind4 -0.3 tvdd+0.3 v analog input voltage ( lin1+/1-/2+/2-, rin1+/1-/2+/2- pins ) vina1 -0.3 avdd1+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 6. vss1-7 must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1-7=0v; note 6 ) parameter symbol min typ max units power supply ( table 4 , note 8 ) tvdd dvdd1 dvdd2 dvdd3 avdd1 avdd2 avdd3 pvdd 3.0 4.75 4.75 4.75 4.75 4.75 4.75 3.0 3.3 5.0 5.0 5.0 5.0 5.0 5.0 3.3 5.25 5.25 5.25 5.25 5.25 5.25 5.25 3.6 v v v v v v v v note 7. the avdd1, avdd2, avdd3, dvdd1, dvdd2 and dvdd3 must be the same voltage. the tvdd must not exceed any of avdd1, avdd2, avdd3, dvdd1, dvdd2 and dvdd3 voltage. note 8. the power-up sequences of avdd1-3, dvdd1-3, pvdd and tvdd are not important. all power supply pins must be up when the pdn pin= ?l?. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4685] ms1106-e-00 2009/08 - 9 - analog characteristics (ta=25 c; tvdd = 3.3v; dvdd1-3=avdd1-3= 5.0v; pvdd = 3.3v; vss1-7 = 0v; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency = 20hz 20khz at fs=48khz, 20hz~40khz at fs=96khz; 20hz~40khz at fs=192khz, all blocks are synchronized, unless otherwise specified) parameter min typ max units adc characteristics feedback resistance 10 50 k resolution 24 bits s/(n+d) (-1dbfs. note 9 ) fs=48khz 82 95 db dr (-60dbfs. note 9 ) fs=48khz, a-weighted 93 102 db s/n (input off) fs=48khz, a-weighted 93 102 db interchannel isolation ( note 10 ) 90 100 db interchannel gain mismatch 0.6 db gain drift 50 - ppm/ c input range (pre-amp output) = 3.3 x avdd1/5 2.97 3.3 3.63 vpp power supply rejection ( note 12 ) 60 db dac to analog output charact eristics (differential mode) resolution 24 bits s/(n+d) (0dbfs) fs=48khz fs=96khz fs=192khz 82 - - 95 95 95 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 98 - - - - 107 102 107 102 107 db db db db db s/n (?0? data) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 98 - - - - 108 102 107 102 107 db db db db db interchannel isolation 90 100 db interchannel gain mismatch 0.5 db gain drift 50 - ppm/ c output voltage (aout+ -aout-)= 2.56 x avdd2/5 2.30 2.56 2.82 vpp load resistance (ac load, note 11 ) 5 k load capacitance 30 pf power supply rejection ( note 12 ) 50 db dac to analog output charact eristics (single end mode) resolution 24 bits s/(n+d) (0dbfs) fs=48khz fs=96khz fs=192khz 80 - - 90 90 90 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 98 - - - - 105 99 105 99 105 db db db db db s/n (?0? data) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 98 - - - - 106 99 105 99 105 db db db db db interchannel isolation 90 100 db interchannel gain mismatch 0.5 db
[ak4685] ms1106-e-00 2009/08 - 10 - gain drift 50 - ppm/ c output voltage aout+ = 2.83 x avdd2/5 2.54 2.83 3.12 vpp load resistance (ac load. note 11 ) 5 k load capacitance 30 pf power supply rejection ( note 12 ) 50 db dac to headphone output (hpl , hpr pin) characteristics ( note 13 ) s/(n+d) (0dbfs. note 14 ) (-6dbfs. note 14 ) 40 60 60 66 db db s/n (?0? data, a-weighted) 88 98 db interchannel isolation 60 80 db interchannel gain mismatch 0.8 db output voltage aout= 1.21 x avdd3/5 ( note 15 ) 1.21 vrms load resistance ( note 16 ) 32 load capacitance 300 pf power supply rejection ( note 12 ) 50 db note 9. when 33khz is input to the external input resistor (ri), 36khz is input to the feed back resistor (rf) and +/-2.70vpp(-1db) or +/-0.003vpp (-60db) is input to the differential input ports. ainl1+ ainl1- rf lampo1 lvcom1 lin1+ lin1 - pr e -amp - + rf ri ri figure 1. adc input circuit note 10. this value is the inter-channel isolation between all the channels of the lin1-2 and rin1-2. note 11. load resistance via an ac coupling resistor. note 12. psr is applied to avdd1, avdd2, avdd3, dvdd1, dvdd2, dvdd3 and pvdd with 1khz, 50mvpp. note 13. 6.8 resistors should be connected in direct to the headphone output pins. when fs=48khz, 96khz or 192khz, the measurement frequency of headphone output is 20hz ~ 20khz. note 14. when load resistance=6.8 +32 . note 15. 1.21vrms (typ) is output to the output pin. when load resistance = 6.8 + 32 , 1vrms (typ) is output at 32 output port. note 16. a more than 32 device can be connected after a 6.8 resistor in direct.
[ak4685] ms1106-e-00 2009/08 - 11 - power supplies parameter min typ max units power supply current normal operation (pdn pin = ?h?) tvdd ( note 17 ) dvdd1+avdd1 dvdd2+avdd2 differential mode fs=48khz fs=96khz fs=192khz single end mode fs=48khz fs=96khz fs=192khz dvdd3+avdd3 (no input) fs=48khz fs=96khz fs=192khz pvdd power-down mode (pdn pin = ?l?; note 18 ) tvdd dvdd1+avdd1 dvdd2+avdd2 dvdd3+avdd3 pvdd 6 33 13 14 17 14 15 18 20 21 23 6 10 10 10 10 10 9 47 19 - - - - - 30 - - 9 100 100 100 100 100 ma ma ma ma ma ma ma ma ma ma ma ma a a a a a note 17. master mode. mcb=36.864mhz. 20pf load capacitors are connected to mcko, bickb, lrckb, sdtob1 and sdtob2 pins. note 18. all digital inputs including clock pins (mclka, mcb, mclkc, bicka, bickb, bickc, lrcka, lrckb, lrckc, sdtia, sdtic) are held at dvdd1, dvdd2, dvdd3, vss1, vss2 or vss7. filter characteristics (ta=-20 c ~+85 c; tvdd=3.0 ~ 5.25v; dvdd1-3=avdd1-3=4.75 ~ 5.25v; pvdd=3.0 ~ 3.6v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 19 ) 0.1db -0.2db -3.0db pb 0 - - 20.0 23.0 18.9 - - khz khz khz stopband sb 28.0 khz stopband attenuation sa 68 db group delay ( note 20 ) gd 16 1/fs adc digital filter (hpf): frequency response ( note 19 ) -3db -0.1db fr 1.0 6.5 hz hz dac digital filter: passband ( note 19 ) 0.1db -6.0db pb 0 - 24.0 21.8 - khz khz stopband sb 26.2 khz stopband attenuation sa 54 db group delay ( note 20 ) gd 20 1/fs dac digital filter + analog filter: frequency response: 0 20.0khz 40.0khz ( note 21 ) 80.0khz ( note 21 ) fr fr fr 0.2 0.3 1.0 db db db note 19. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs (dac). the reference frequency of these responses is 1khz.
[ak4685] ms1106-e-00 2009/08 - 12 - note 20. the calculating delay time occurre d at digital filtering. this time is fro m setting the input of analog signal to setting the 24bit data of both channels to the output register of portb. for dac, this time is from setting the 20/24bit data of both channels on input registers of porta and portc to the output of analog signal. note 21. 40.0khz@fs=96khz, 80.0khz@fs=192khz.
[ak4685] ms1106-e-00 2009/08 - 13 - dc characteristics (ta=-20 c ~+85 c; tvdd=3.0 ~ 5.25v; dvdd1-3 = 4.75 ~ 5.25v, avdd1-3=4.75 ~ 5.25v; pvdd=3.0 3.6v) parameter symbol min typ max units high-level input voltage (except xti pin) (xti pin) low-level input voltage (except xti pin) (xti pin) vih vih vil vil 2.2 70%dvdd1 - - - - - - - - 0.8 30%dvdd1 v v v v input voltage at ac coupling (xti pin) ( note 22 ) vac 40%dvdd1 - - vpp high-level output voltage (iout=-400 a. except xto pin) low-level output voltage (iout=400 a. except xto pin or sda pin, 3ma(sda pin)) voh vol tvdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 a note 22. this is the va lue when a capacitor (0.1 f) is connected to the xti pin. switching characteristics (ta=-20 c ~+85 c; tvdd=3.0 ~ 5.25v; dvdd1-3=avdd1-3=4.75 ~ 5.25v; pvdd=3.0 3.6v; c l = 20pf (except for sda pin), cb=400pf(sda pin)) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 24.576 mhz external clock frequency duty feclk declk 8.192 40 50 36.864 60 mhz % mcko output frequency duty fmck dmclk 8.192 40 50 36.864 60 mhz % master clock ( note 23 ) 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high 768fsn, 384fsd, 192fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 24.576 10 10 12.288 18.432 24.576 36.864 mhz ns ns mhz ns ns mhz ns ns mhz ns ns lrcka/b/c timing (slave mode) normal speed mode double speed mode (lrck a, lrck c) quad speed mode (lrck a, lrck c) duty cycle fsn fsd fsq duty 32 64 120 45 48 96 192 55 khz khz khz % lrckb timing (master mode) lrckb frequency duty cycle fs duty 32 50 48 khz %
[ak4685] ms1106-e-00 2009/08 - 14 - parameter symbol min typ max units audio interface timing (slave mode) porta, c bicka,c period bicka,c pulse width low pulse width high lrcka,c edge to bicka ? ? ( note 24 ) bicka,c ? ? to lrcka edge ( note 24 ) sdtia,c hold time sdtia,c setup time tbck tbckl tbckh tlrb tblr tsdh tsds 81 32 32 20 20 10 10 ns ns ns ns ns ns ns portb bickb period bickb pulse width low pulse width high lrckb edge to bickb ? ? ( note 24 ) bickb ? ? to lrckb edge ( note 24 ) lrckb to sdtob1,2 (msb) bickb ? ? to sdtob1,2 tbck tbckl tbckh tlrb tblr tlrs tbsd 324 128 128 80 80 80 80 ns ns ns ns ns ns ns audio interface timing (master mode) bickb frequency bickb duty bickb ? ? to lrckb edge bickb ? ? to sdto fbck dbck tmblr tbsd -40 64fs 50 40 20 hz % ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 25 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 - 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf power-down & reset timing pdn pulse width ( note 27 ) pdn ? ? to sdtob1,2 valid ( note 28 ) tpd tpdv 150 522 ns 1/fs note 23. mcb supports only normal mode (256fsn, 384fsn, 512fsn, 768fsn). note 24. bicka/b/c rising edge must not occur at the same time as lrcka/b/c/ edge. note 25. data must be held long enough to bridge the 300ns-transition time of scl. note 26. i 2 c-bud is a trademark of nxp b.v. note 27. the ak4685 is reset by bringing the pnd pin = ?l?. note 28. this is the number of lrckb rising from pdn rising.
[ak4685] ms1106-e-00 2009/08 - 15 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd, 1/fsq lrck vih vil tbck tbckl vih tbckh bick vil 1/fmck tmckl 50%tvdd dmck = tmckl x fmck x 100 mcko clock timing lrck= lrcka, lrckb, lrckc bick= bicka, bickb, bickc sdti= sdtia, sdtic sdto= sdtob1, sdtob2. tlrb lrck vih bick vil tlrs sdto 50% tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing
[ak4685] ms1106-e-00 2009/08 - 16 - lrck bick sdto tbsd tmblr 50% tvdd 50% tvdd 50% tvdd audio interface timing (master mode) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn tpdv sdto 50% tvdd vih power down & reset timing
[ak4685] ms1106-e-00 2009/08 - 17 - operation overview system clock the ak4685 has three audio serial interfaces (porta, po rtb and portc) which can be operated asynchronously. the porta and portc are the audio data interfaces for dac1 and dac2, the portb is for adc. at each port, the external clocks, which are required to operate the ak4685 in slave mode, are mclka, mcb, lrcka/b/c, and bickfa/b/c. the mclka/c and mcb must be synchronized with lrcka/b/c but the phase is not critical. master/slave mode the msb pin selects master/slave mode of portb. porta and portc are slave mode only. in master mode, lrckb pin and bickb pin are output pins. in slave mode, lrcka/b/c pins and bicka/b/c pins are input pins ( table 1 ). the portb is in slave mode at power-down (pdn pin = ?l?). to change it to master mode, set the msb pin to ?h?. until setting the msb pin to ?h?, lrck b and bickb pins are input pins. ar ound a 100kohm pull-up (or down) resistor is required to prevent floating of these input pins. pdn pin msb pin portb (adc) bickb, lrckb porta/c (dac1/2) bicka/c, lrcka/c l input (slave mode) input (slave mode) l h output ?l?(master mode) input (slave mode) l input (slave mode) input (slave mode) h h output (master mode) input (slave mode) table 1. master/salve mode
[ak4685] ms1106-e-00 2009/08 - 18 - cristal oscillator circuit the clock for the mcb/xti pin can be generated by the two methods: 1) x?tal xti xto ak4685 25k note 29. the capacitor value is depend on the crystal oscillator (typ.10-40pf) figure 2. x?tal mode 2) external clock - note: the clock must not over dvdd. xti xto ak4685 25k (input: cmos level) (input: ? 40%dvdd, c=0.1 f) figure 3. direct input figure 4. ac coupled
[ak4685] ms1106-e-00 2009/08 - 19 - adc clock control the integrated adc of the ak4685 operates by the clock from mcb/xti pin. in master mode (msb pin = ?h?), the cks11-0 bits select the clock frequency ( table 2 ). the adc is in power-down mode until mcb is supplied. cksb1 cksb0 clock speed 0 0 256fs (default) 0 1 384fs 1 0 512fs 1 1 768fs table 2. port1 master clock control (adc master mode) in slave mode (msb pin = ?l?), the master clock (mcb) must be synchronized with lrckb but the phase is not critical. after exiting reset state when power-up the device or other s ituations (pdn pin = ?h?), the adc is in power-down mode until mcb is input. lrckb mcb (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - 8.1920 12.2880 16.3840 24.5760 44.1khz - - 11.2896 16.9344 22.5792 33.8688 48.0khz - - 12.2880 18.4320 24.5760 36.8640 normal table 3. system clock example (adc slave mode)
[ak4685] ms1106-e-00 2009/08 - 20 - dac1/2 clock control the master clock mclka (mclkc) must be synchronized with lrcka (lrckc) but the phase is not critical. after exiting reset state when power-up the device or other situations (pdn pin = ?h?), the dac is in power-down mode until mclka/c and lrcka/c are input. there are two modes for controlling the sampling speed of dac1(dac2). one is the manual setting mode (acks bit = ?0?) using the dfs1-0 bits, and the other is auto setting mode (acks bit = ?1?). 1. manual setting mode (acks1(acks2) bit = ?0?) when the acks1(acks2) bit = ?0?, dac1(dac2) is in manual setting mode and the sampling speed is selected by dfs11-10, dfs21-20 bits ( table 4 ). dfs11 (dfs21) dfs10 (dfs20) dac1(dac2) sampling speed fs 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz (default) 1 0 quad speed mode 120khz~192khz 1 1 not available - (note: adc is always in normal speed mode) table 4. dac sampling speed (acks1/2 bit = ?0?, manual setting mode) lrcka/c mclka/c (mhz) bicka/c (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 5. dac system clock example (dac normal speed mode @manual setting mode) lrcka/c mclka/c (mhz) bicka/c (mhz) fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896 16.9344 22.5792 33.8688 5.6448 96.0khz 12.2880 18.4320 24.5760 36.8640 6.1440 table 6. dac system clock example (dac double speed mode @manual setting mode) lrcka/c mclka/c (mhz) bicka/c (mhz) fs 128fs 192fs 256fs 384fs 64fs 176.4khz 22.5792 33.8688 - - 11.2896 192.0khz 24.5760 36.8640 - - 12.2880 table 7. dac system clock example (dac quad speed mode @manual setting mode)
[ak4685] ms1106-e-00 2009/08 - 21 - 2. auto setting mode (acks1/2 bit = ?1?) when the acks1(acks2) bit = ?1?, the dac is in auto setting mode and the sampling speed is selected automatically by the ratio of mclka/lrcka or mclkc/lrckc, as shown in the table 8 and table 9 . in this mode, the settings of dfs21-20 bit or fs11-10 bit are ignored. mclka/c dac1/2 sampling speed (fs) lrcka/c 512fs, 768fs normal speed mode 32khz~48khz 256fs, 384fs double speed mode 64khz~96khz 128fs, 192fs quad speed mode 120khz~192khz (note: adc is always in normal speed mode) table 8. dac sampling speed (acks bit = ?1?, auto setting mode) lrcka/c mclka/c (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.8640 - - - - quad table 9. dac system clock example (auto setting mode) de-emphasis filter the ak4685 includes a digital de-emphasis filter (tc=50/15 s) by iir filter. this filter corresponds to three sampling frequencies (32khz, 44.1khz, 48khz). de-emphasis filter is off in double speed mode and quad speed mode. de- emphasis of each dac can be se t individually by register. mode sampling speed dem21/dem11 dem20/dem10 dem 0 normal speed 0 0 44.1khz 1 normal speed 0 1 off 2 normal speed 1 0 48khz 3 normal speed 1 1 32khz (default) table 10. de-emphasis control
[ak4685] ms1106-e-00 2009/08 - 22 - adc digital high pass filter the integrated adc has a digital high pa ss filter for dc offset cancelling. the cut-off frequency is 1.0hz at fs=48khz and scales with sampling rate (fs). audio serial interface format each porta/b/c can select independent audio interface format. difa1-0 bits control the porta. the msb pin and difb bit control portb. in all modes, the serial data is msb first, 2?s complement fo rmat. the sdtob1/2 pins are clocked out on the falling edge of bickb pin and the sdtia/c pins are latched on the rising edge of bicka/c pins. ?0? should be written to lsb bits wit hout data on each sdtia/c input. 1. porta/c setting the difa1-0 bits and difc1-0 bits select following four serial data formats ( table 11 ). lrcka bicka mode difa1 (difc1) bit difa0 (difc0) bit sdtia1 l/r i/o speed i/o 0 0 0 20bit, right justified h/l i 48fs i 1 0 1 24bit, right justified h/l i 48fs i 2 1 0 24bit, left justified h/l i 48fs i 3 1 1 24bit, i 2 s l/h i 48fs i (default) table 11. audio interface format 2. portb setting 2-1: normal mode: msb pin and difb bit select following four serial data formats ( table 12 ). lrcka bicka mode msb pin difb bit sdtob1,2 l/r i/o speed i/o 0 l 0 24bit, left justified h/l i 48fs i 1 l 1 24bit, i 2 s l/h i 48fs i (default) 2 h 0 24bit, left justified h/l o 64fs o 3 h 1 24bit, i 2 s l/h o 64fs o (default) table 12. audio interface format
[ak4685] ms1106-e-00 2009/08 - 23 - lrck bick(64fs) sdto(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 5. audio data timing (sdto: mode0/2, sdti: mode0) lrck bick(64fs) sdto(o) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 6. audio data timing (sdto: mode0/2, sdti: mode1) lrck bick(64fs) sdto(o) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 2 3:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 2 1 28 2 9 30 0 figure 7. audio data timing (sdto: mode0/2, sdti: mode2) lrck bick(64fs) sdto(o) 0 1 2 3 22 23 24 25 0 0 1 sdti(i) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 8. audio data timing (sdto: mode1/3, sdti: mode3)
[ak4685] ms1106-e-00 2009/08 - 24 - digital volume control the ak4685 has channel-independent digital volume control ( 256 levels, 0.5db step). the iatl7-0, iatr7-0 bits set the volume level of adc channel ( table 13 ). the oat1l7-0, oat1r7-0, oat2l7- 0 and oat2r7-0 bits set each dac channel ( table 14 ). iatl7-0, iatr7-0 gain 00h +24db 01h +23.5db 02h +23.0db : : 2fh +0.5db 30h 0db 31h -0.5db : feh -103db ffh mute (- ) (default) table 13. adc digital volume (iatt) oat1l7-0, oat1r7-0, oat2l7-0, oat2r7-0 gain 00h +12db 01h +11.5db 02h +11.0db : : 17h +0.5db 18h 0db 19h -0.5db : feh -115db ffh mute (- ) (default) table 14. dac digital volume (oatt) atsad (atsda) bits ( table 15 , table 16 ) control the transition time of attenuation. the transition between each attenuation level is the soft transition. therefore, the switching noise does not occur in the transition. mode atsad att speed 0 0 1061/fs 1 1 256/fs (default) table 15. transition time of attenuation (adc) mode atsda att speed 0 0 1061/fs 1 1 256/fs (default) table 16. transition time of attenuation (dac1/2)
[ak4685] ms1106-e-00 2009/08 - 25 - the transition between set values is soft transition of 1061 levels in mode 0. it takes 1061/fs (22ms@fs=48khz) from 00h to ffh(mute). if the pdn pin goes to ?l?, the iatl7-0, iatr7-0 (oat1l7-0, oat1r7-0, oat2l7-0, oat2r7-0) bits are initialized to 30h(18h). the att levels go to their default value when rstn bit = ?0?. when rstn bit return to ?1?, the atts fade to their current value. digital soft mute the adc and dac have a soft mute function. the soft mute operation is performed at digital domain. when the smad/smda bits go to ?1?, the output signal is attenuated by - during att_data att transition time ( table 15 , table 16 ) from the current att level. when the smad/smda bits are returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level in the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smad/smda bits attenuation att level - aout gd gd (1) (2) (3) (1) notes: (1) att_data att transition time ( table 15 , table 16 ). for example, in normal speed mode, this time is 1061/fs cycles (256/fs) at att_data=00h. att trans ition of the soft-mute is from 00h to ffh (2) the analog output corresponding to the digital input has group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level in the same cycle. figure 9. soft mute function
[ak4685] ms1106-e-00 2009/08 - 26 - pre-amp and differential inputs the input atts are constructed by connecting input resistors (ri) to lin1+/- pins and feedback resistors (rf) between lampo1/ lvcom1 pin and lin1-/lin1+ pin ( figure 10 ). the input voltage range of the lampo1/ lvcom1 pin is typically +/- 0.33 x avdd (vpp). if the i nput voltage of the input selector exceeds typ. +/- 5.66vpp (+/- 2vrms differential), or +/-8.48vpp(+/- 3vrms differential), the input voltage of the lampo1/ lvcom1 pins must be attenuated to typ. +/-3.3 x avdd1/5 (vpp) atts. table 17 shows ri and rf constant examples. ainl1+ ainl1- rf lampo1 lvcom1 lin1+ lin1 - pr e- am p - + rf ri ri figure 10. external connection example (differential input) input range ri [k ] rf [k ] att gain [db] voltage between lampo1 and lvcom1 pins +/-8.48vpp (+/-3vrms differential input) 47 18 ?8.3 +/-3.25vpp +/-5.66vpp (+/-2vrms differential input) 33 18 ?5.3 +/-3.08vpp +/-2.83vpp (+/-1vrms differential input) 16 18 +1.02 +/-3.18vpp note 30. the input range of the internal adc is +/-3.3 x avdd1/5 vpp typ. note 31. the input range is the voltage difference of ri inputs (ainl1/l2/r1/r2+)-(ainl1/l2/r1/r2-). table 17. input att example (differential input)
[ak4685] ms1106-e-00 2009/08 - 27 - (pseudo cap-less /single-ended input) the input atts are constructed by connecting input resistors (ri) to lin1+/- pins and feedback resistors (rf) between lampo1/ lvcom1 pin and lin1-/lin1+ pin ( figure 11 ) when using single-ended and pseudo cap-less inputs as well as when using differential inputs. the input voltage range of the lampo1/ lvcom1 pin is typically +/- 0.33 x avdd (vpp). if the input voltage of the input selector exceeds typ. 5.66vpp (2vrms) or 8.48vpp (3vrms), the input voltage of the lampo1/ lvcom1 pins must be attenua ted to typ. +/-3.3 x avdd1/5 (vpp) atts. table 18 shows ri and rf constant examples. gnd ainl1 rf lampo1 lvcom1 lin1+ lin1 - pr e- am p - + rf ri ri figure 11. external connection example (single-ended input) input range ri [k ] rf [k ] att gain [db] voltage between lampo1 and lvcom1 pins 8.48vpp (3vrms) 47 36 ?2.3 +/-3.25vpp 5.66vpp (2vrms) 33 36 +0.7 +/-3.08vpp 2.83vpp (1vrms) 16 36 +7.02 +/-3.18vpp note 32. the input range of the internal adc is +/-3.3 x avdd1/5 vpp typ. note 33. the input range is the voltage difference of ri inputs (ainl1/l2/r1/r2)-gnd. table 18. input att example (single-end input)
[ak4685] ms1106-e-00 2009/08 - 28 - analog outputs (differential mode) the analog outputs are fully differentia l outputs when the sgl pin = ?l?, a nd the output range is 2.56 x (avdd2)/5 vpp centered around analog common voltage (vcom pin). the differential outputs are summed externally. the summing gain between l/rout+ and l/rout- is v l/rout = (l/rout+)-(l/rout-). if the summing gain is 1.09, the output range is 5.59vpp (typ@vdd=5v). the bias voltage of the external summing circuit is supplied externally. the output voltage (v aout ) is positive full scale for 7fffffh (@24-bits) and negative full scale for 800000h (@24-bits). the ideal v aout is 0v for 000000h(@24-bits). the internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulat or beyond the audio passband. figure 12 and figure 13 show examples of an external lpf circuit summing the differential outputs with an op-amp. 7.5k 8.2k r1 7.5k r1 8.2 k 270p vop 270p vop 1k 1k 47u 0.1u bias l/rout- l/rout+ 2200p when r1=300 figure 12. external 2 nd order lpf circuit example (using op-amp with single power supply) 7.5k 8.2k r1 7.5k r1 8.2 k 270p +vop 270p -vop l/rout- l/rout+ 2200p when r1=300 figure 13. external 2 nd order lpf circuit example (using op-amp with dual power supplies) (single-ended mode) the analog outputs are single-ended when the sgl pin = ?h? and the signals are output from the l/rout+ pins. in this case, the l/rout- pins should be ope ned. the output range is 2.8 x (avdd2)/5 vpp (typ) centered around the analog common voltage (vcom pin).
[ak4685] ms1106-e-00 2009/08 - 29 - charge pump circuit the internal charge pump circuit generates negative volta ge (pvee) from pvdd voltage for headphone amplifiers. the internal charge pump starts operation when pwda2 bit = ?1?. the power up time of charge pump circuit is maximum 8.0ms. when pwhp bits = ?1?, the headphone-amp is powered-up after the charge pump circuit is powered-up. headphone-amp (hpl/hpr pins) power supply voltage for headphone amplifiers is applied from a regulator for positive power and a charge-pump for negative power. the regulator is driven by avdd3 and the charge-pump is driven by pvdd. the pvee pin outputs the negative voltage generated by the internal charge pump ci rcuit. the headphone amplifier output is single-ended and centered on 0v (vss5). therefore, the capacitor for ac-coup ling can be removed. the minimum load resistance is 32 . when the dac input signal level is 0dbfs, the output voltage is 1.21vrms (= 31mw @ 32 via 6.8ohm resistor) at hpga4-0 bits = 0db. the output level of headphone-amp can be controlled by hpga4-0 b its. this volume setting is common to l/r channels and can attenuate / gain the mixe r output from +12db to ?50db in 2db step. when changing the volume, pop noise occurs. hpga4-0 bits gain (db) step 1fh +12 1eh +10 : : 1ah +2 19h 0 (default) 18h ? 2 17h ? 4 16h ? 6 : : 2h ? 46 1h ? 48 0h ? 50 2db table 19. headphone-amp volume setting when pwhp bit is ?1?, the headphone-amps are powered-up. the headphone output is enabled when hpmtn bit is ?1? and muted when hpmtn bit is ?0?. the mute on/off time is set by pts1-0 bits when moff bit is ?0?. mute on/off time pts2 pts1 pts0 typ. max. 0 0 0 (reserved) (reserved) 0 0 1 (reserved) (reserved) 0 1 0 4.1ms 6.9ms 0 1 1 8.2ms 13.9ms 1 0 0 16.4ms 27.7ms (default) 1 0 1 32.8ms 55.4ms 1 1 0 65.6ms 100.8ms 1 1 1 131.2ms 221.6ms table 20. headphone-amp mute on/off transition time
[ak4685] ms1106-e-00 2009/08 - 30 - soft transition enable/disable is controlled by moff bit. when this bit is ?1?, soft transition is disabled and the headphone is switched on/off immediately. when soft transition is enabled, a register setting of the address 0bh should be made in an interval more than soft transition time. register writings ar e ignored if the same value is written to these registers. when pwhp bit is ?0?, the headphone-amps are powered-down completely. at that time, the hpl and hpr pins go to vss5 voltage via the internal pulled-down resistor. the pulled-down resistor is 20 (typ) at hpz bit = ?0?, 50k (typ) at hpz bit = ?1?. the power-up time is 16.4ms (typ.) and 27.7ms (max.), and power up/down is executed immediately. pwhp hpz pwda2 hpmtn mode hpl/r pin states 0 0 x x power-down & mute pulled-down by 20 (typ) (default) 0 1 0 x n/a n/a 0 1 1 x power-down pull-down by 50k (typ) 1 x 0 x n/a n/a 1 x 1 0 mute vss5 1 x 1 1 normal operation normal operation table 21. headphone outputs status (x: don?t? care) clock stop detection function when mclka, mcb and mclkc external clocks are st opped, corresponding digital blocks become power-down mode. the power-down mode is released automatically and digital bl ocks return to normal operation when external clocks are supplied again. an initialization cycle of 522/fs is taken before returning to normal operation when mcb clock is stopped.
[ak4685] ms1106-e-00 2009/08 - 31 - analog mute when the mt1n pin is set to ?l? from ?h?, a digital to analog data converting is stropped and the analog outputs (lout+/-, rout+/- pins) are attenuated in soft transition. the analog block becomes power-down mode after the soft transition is completed, and vcom is output from the analog outputs. transition time is controlled by amt2-0 bits. when the mt1n pin is set to ?h? from ?l?, the analog block returns to normal operation and a digital to analog converting is resumed. after dac initializing time, the mute is cancelled and the output atte nuation gradually changes to the att level during att_data x att transition time. ( table 16 ) normal operation init cycle mt1n pin gd (3) (1) (2) digital attenuation dacl+/-, dacr+/- att level - 512/fs power (1) ?l? time of 20ms or more is needed. (2) the soft mute transition time by analog processing is depending on the amt2-0 bits setting. a crick noise occurs when each power supply (tvdd, dvdd1/2/3, avdd1/2/3 and pvdd) is off during mute transition time. power supplies should be provided longer than the tr ansition time set by amts2-0 bits set. (3) att_data x att transition time ( table 16 ). in case of mode0 and ats2-0 bits =?00h?, the transition time of att value from ffh(0db) to 00h(mute) is 1061/fs. figure 14. mute sequence example (mt1n pin) when the mt2n pin is set to ?l? from ?h?, the headphone output is attenuated in soft transition. the analog and headphone blocks become power-down mode after the soft transition is comple ted, and ground level (vss5) is output from these outputs. transition time is controlled by amt2-0 bits. the data inputs and dac clocks must not be stopped before the soft transition complete. when the mt2n pin is set to ?h? from ?l?, the analog and headphone blocks return to normal operation and a digital to analog converting is resumed. after dac initializing time, the mute is cancelled and th e output attenuation gradually changes to the att level during att_data x att transition time. ( table 16 )
[ak4685] ms1106-e-00 2009/08 - 32 - normal operation init cycle mt2n pin (3) (1) digital attenuation (2) hdp out att level - dac internal state 512/fs hdp state power down hpmtn operation mute hpmtn operation normal operation normal operatio n (5) (6) (4) power (1) ?l? time of 20ms or more is needed. (2) the mute time of the headphone amplifier is 8.2ms (typ) and 14ms (max) when ptsa bit = ?0? (at default pts2-0 bits = ?011?). pst2-0 bits setting does not effect this mute time. the mute time can be controlled by pts2-0 bits setting when ptsa bit = ?1?. a crick noise occurs when each power supply (tvdd, dvdd1/2/3, avdd1/2/3 and pvdd) is off during mute transition time. power supplies should be provided longer than the transiti on time set by amts2-0 bits set. (3) att_data x att transition time ( table 16 ). in case of mode0 and ats2-0 bits =?00h?, the transition time of att value from ffh(0db) to 00h(mute) is 1061/fs. (4) power down time of the headphone amplifier is controlled by amts2-0 bits. the amts2- 0 bits setting value should be shorter than pts2-0 bits setting value. (5) headphone amplifier power-up: gnd level is output when the headphone amplifier is muted. the headphone amplifier power-up time is 27.7ms (max). (6) the mute release time of the headphone amplifier is controlled by pts2-0 bits or moff bit settings. figure 15. mute sequence example (mt2n pin)
[ak4685] ms1106-e-00 2009/08 - 33 - amts2-0: analog mute power-down time control power-down time amts 2 amts 1 amts 0 typ. max. 0 0 0 10ms 17ms (default) 0 0 1 21ms 35ms 0 1 0 41ms 70ms 0 1 1 82ms 140ms 1 0 0 164ms 280ms 1 0 1 5.1ms 8.6ms 1 1 x 1.3ms 2.2ms table 22. power-down time control
[ak4685] ms1106-e-00 2009/08 - 34 - l/r channels of the analog outputs (lout+/-, rout+/- pins) can be muted independently by amt1ln or amt1rn bits = ?0?. when those channels are muted, transition time is depending on amt2-0 bits setting. each mute is cancelled by amt1ln / amt1rn bit = ?1?. it is digitally-processed, and the output attenuation gradually changes to the att level during att_data x att transition time. ( table 16 ) amt1ln/1rn bit (3) (1) gd (2) digital attenuation aout att level - (1) ?l? time of 20ms or more is needed. (2) the soft mute transition time by analog processing is depending on the amts2-0 bits setting. (3) att_data x att transition time ( table 16 ). in case of mode0 and ats2-0 bits =?00h?, the transition time of att value from ffh(0db) to 00h(mute) is 1061/fs. figure 16. mute sequence example (amt1ln/1rn bit) when amt1ln=amt1rn bit = ?0?, the analog outputs (dacl+/-, dacr+/- pins) are attenuated in soft transition as well as when the mt1n pin = ?l?. the analog block becomes power-down mode after the soft transition is completed, and vcon is output from the analog outputs. when a one of or both amt1l and amt1rn bits are set to ?1?, the analog block returns to normal operation. the mute on the corresponding channel is cancelled and the output a ttenuation gradually changes to the att level during att_data x att transition time. ( table 16 ) when the amt2ln=amt2rn bit = ?0?, the analog and h eadphone blocks become powe r-down mode, and ground level (vss5) is output from these outputs as well as when the mt2n pin = ?l?. transition time is controlled by amt2-0 bits. the data inputs and dac clocks must not be stopped before the soft transition complete. when t both amt2l and amt2rn bits are set to ?1?, the analog and headphone blocks return to normal operation. the mute is cancelled and the output attenuation gradually ch anges to the att level during att_data x att transition time. ( table 16 )
[ak4685] ms1106-e-00 2009/08 - 35 - power on/off sequence the each block of the ak4685 is placed in power-down mode by bringing the pdn pin ?l? and both digital filters are reset at the same time. the pdn pin =?l? also reset the cont rol registers to their default values. in power-down mode, the dac1/2 outputs go to vss3/5 and the sdtob1/2 pins go to ?l?. the ak4685 should be powered-up when the pdn pin = ?l? to reset the internl registers. in slave mode, after exiting reset at power-up or other situations, the adc/dac1/dac2 starts operation on the rising edge of lrckb/a/c after mcb/mlcka/ c inputs. the adc is in power-dow n mode until mcb is input, and the dac1/2 are in power-down mode un til mlcka/c or lrcka/c is input. the analog initialization cycle of adc starts after exiting th e power-down mode. therefore, the output data, sdtob1/2 becomes available after 522/fs cycles of lrckb clock. in cas e of the dac1/2, an analog in itialization cycle starts after exiting the power-down mode. the analog outputs are vss3/5 during the initialization. figure 17 shows the sequences of the power-down and the power-up. the adc and dac?s can be powered-down individually by pwad and pwda1/2 bits. these bits do not initialize the internal register values. when pwad b it = ?0?, the sdtob1/2 pins go to ?l ?. when pwda1 bit = ?0?, the analog outputs (lout+/-, rout+/- pins) go to vcom voltage. when pwda2 bit = ?0?, the headphone outptus (hpl/r pins) go to vss5 voltage. as some click noise occurs, the analog output should be muted externally if the click noise influences a system application. a dc internal state pdn clock in mclk,lr ck,bick a dc in (analog) a dc out (digital) dac internal state dac in (digital) dac out (analog) external mute mute on (14 ) power po we r-do wn don?t care gd ?0 ?d ata po we r-do wn ?0 ?d ata gd (5) (3) (6) (8 ) 522/fs init cycle normal operation (3) gd normal operation gd (7) (8 ) 512/ fs init cycle (4) mu te on ?0?data ?0 ?d ata don?t care (8) hpl/hpr pins (2) (1 ) (12) pwhp bit ( 10) (1 3) hpmtn pin 0v pvee 0v normal mute mute (11) 0v 0v (9) pwda2 bit pvee pin figure 17. power-up/down sequence example
[ak4685] ms1106-e-00 2009/08 - 36 - notes: (1) the pdn pin should be set ?l? ? ?h? after the all powers (tvdd, dvdd1/2/3, avdd1/2/3 and pvdd) are supplied. the ak4685 requires 150ns or longer ?l? period fo r a reset. the ak4685 should be powered-up when the pdn pin = ?l?. (2) power-on the regulator, charge pump circu it, vcom, hp-amp and internal oscillator: the pvee pin becomes to the same voltage as pvee within 8.0ms (max). (3) the analog block of the adc is initialized after exiting the power-down state. (4) the analog block of the dac is initialized after exiting the power-down state. (5) the digital outputs corresponding to analog inputs, and the analog outputs corresponding to digital inputs have group delay (gd). (6) adc output is ?0? data at the power-down state. (7) click noise occurs at the end of initialization of the analog block. mute the digital outputs externally if the click noise influences a system application. (8) a click noise occurs at the falling edge of pdn and at 512/fs after the rising edge(after charge-pump is power-on) of pdn. (9) power-up of headphone-amp: pwhp bit = ?0? ? ?1? headphone-amp is in mute state and outputs ground level. headphone-amp power-up time is 27.7ms (max.). (10) headphone-amp mute release: hpmtn pin = ?l? ? ?h? headphone-amp goes to the normal operation after the transition time. headphone-amp mute release time depends on the setting of pts1-0 and moff bits. (11) headphone-amp mute: hpmtn pin = ?h? ? ?l? headphone-amp goes to mute state after the tr ansition time set by pts1-0 and moff bits. (12) headphone-amp power-down: pwhpl/r bits = ?1? ? ?0? headphone-amp is powered-down immediately. (13) pwda2 bit = ?1? ? ?0? the pvee pin becomes 0v according to the time constant of the capacitor at the pvee pin and the internal resistor. the internal resistor is 17.5k (typ.). (14) mute the analog outputs externally if the click noise (8) influences a system application.
[ak4685] ms1106-e-00 2009/08 - 37 - reset function when rstn bit = ?0?, the adc and dac digital blocks are powered-down but the internal register are not initialized. the analog outputs (lout+/-, rout+/- pins) go to vcom voltage, the headphone outputs (hpl/r pins) go to ground level (vss5) and the sdtob1/2 pins go to ?l?. as some clic k noise occur, the analog outputs should be muted externally if the click noise influences a system application. the figure 18 shows the power-up sequence. a dc internal state rstn bit normal operat ion digital block power-down normal operat ion gd gd a dc in (analog) ?0?data a dc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac ou t (analog) gd gd (2) (2 ) (3) (4 ) (6) (6) internal rstn bit digital block power-down 1~2/fs 4~5/fs (7) (5) 516/fs init cycle (1) notes: (1) the analog block of adc is initialized after exiting the reset state. (2) the digital outputs corresponding to the analog inputs, and the analog outputs corresponding to the digital inputs have group delay (gd). (3) adc output is ?0? data at power-down state. (4) click noise occurs when the internal rstn bit becomes ?1?. mute the digital outputs externally if the click noise influences a system application. (5) when rstn bit = ?0?, the analog outputs go to 0v. (6) a click noise occurs at 4 5/fs after rstn bit became ?0?, and occurs at 1 2/fs after rstn bit becomes ?1?. (7) there is a delay about 4~5/fs from a writing ?0? to th e rstn bit until the internal rstn bit changes to ?0?. figure 18. reset sequence example
[ak4685] ms1106-e-00 2009/08 - 38 - serial control interface the ak4685 supports fast-mode i 2 c-bus system (max: 400khz). 1. data transfer all commands are preceded by start condition. after the st art condition, a slave addre ss is sent. after the ak4685 recognizes start condition, the device inte rfaced to the bus waits for the slave address to be transmitted over the sda line. if the transmitted slave address matches an address for one of the devices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminated by stop conditi on generated by the master device. 1-1. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable : data valid change of data a llowed figure 19. data transfer 1-2. start and stop condition a high to low transition on the sda line while scl is high indicates start condition. all sequences start from start condition. a low to high transition on the sda line while scl is high defines stop condition. all sequences end by stop condition. scl sda stop condition start condition figure 20. start and stop conditions
[ak4685] ms1106-e-00 2009/08 - 39 - 1-3. acknowledge acknowledge is a software convention used to indicate successful data tr ansfers. the transmitting device will release the sda line (high) after transmitting eight b its. the receiver must pull down the sda line during the acknowledge clock pulse so that sda remains stable ?l? during ?h? period of this clock pulse. the ak4685 will generates an acknowledge after each byte has been received. in read operation, the slave, the ak4685 w ill transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by th e master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await stop condition. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 21. acknowledge on the i 2 c-bus 1-4. first byte the first byte, which includes seven bits of slave address a nd one bit of r/w bit, is sent after start condition. if the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the sda line. the most significant seven bits of the slave address are fixed as ?0010010?. the eighth bit (lsb) of the first byte (r/w bit) defines whether a write or read condition which the master requests. ?1? indicates that the read operation is to be executed. ?0? indicates that the wr ite operation is to be executed. 0 0 1 0 0 1 0 r/w figure 22. the first byte
[ak4685] ms1106-e-00 2009/08 - 40 - 2. write operations set r/w bit = ?0? for the write operation of the ak4685. after receipt of the start condition and the first byte, the ak4685 generates an acknowledge, and awaits the second byte (register address). the second byte consists of the address fo r control registers of ak4685. the format is msb first, and those most significant 3-bits are ?don?t care?. * * * a4 a3 a2 a1 a0 (*: don?t care) figure 23. the second byte after receipt of the second byte, the ak 4685 generates an acknowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 24. byte structure after the second byte the ak4685 is capable of more than one byte write operation in one sequence. after a receipt of the third byte, the ak4685 generates an ac knowledge, and awaits the next data again. the master can transmit more than one word inst ead of terminating the write cycle after the firs t data word is transferred. after the receipt of each data, the internal 5bits address counter is incremented by one, and the ne xt data is taken into next address automatically. if the address exceeds 0ch prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave a ddress a c k register a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 25. write operation
[ak4685] ms1106-e-00 2009/08 - 41 - 3. read operations set r/w bit = ?1? for the read operation of the ak4685. the master can read next address?s data by generating the acknowledge instead of terminating the write cycle after the receipt of the first data word. after the receipt of each data, the internal 5bits a ddress counter is incremented by one, and the next data is taken into next addr ess automatically. if the address exceeds 0c h prior to generating stop condition, the address counter will ?roll over? to 00h a nd the previous data will be overwritten. the ak4685 supports two basic read operations : current address read and random read. 3-1. current address read the ak4685 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit set to ?1?, the ak4685 generate s an acknowledge, transmits 1byte data which address is set by the internal address counter and incr ements the internal address counter by 1. if the master does not generate an acknowledge to th e data but generate stop condition, the ak4685 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 26. current address read 3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues start condition, slave address(r/w bit=?0?) and then the regist er address to read. after the register address?s acknowledge, the master immediat ely reissues the start condition and the slave address with the r/w bit set to ?1?. then the ak4685 generates an acknowledge, 1byte data a nd increments the internal address counter by 1. if the master does not generate an acknowle dge but generate the stop condition, the ak4685 discontinues transmission. sda s t a r t a c k a c k s s s t a r t slave a ddress word a ddress(n) slave a ddress a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 27. random read
[ak4685] ms1106-e-00 2009/08 - 42 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown pwhp pwda2 pwda1 pwad smda2 smda1 smad rstn 01h analog mute 0 0 0 0 amt2rn amt2ln amt1r amt1l 02h interface control cksb1 cksb0 difc1 difc0 difb 0 difa1 difa0 03h dac speed control 0 acks2 dfs21 dfs20 0 acks1 dfs11 dfs10 04h de-emphasis/ att speed dem21 dem20 dem11 dem10 0 0 atsad atsda 05h adc lch volume iatl7 iatl6 iatl5 iatl4 iatl3 iatl2 iatl1 iatl0 06h adc rch volume iatr7 iatr6 i atr5 iatr4 iatr3 iatr2 iatr1 iatr0 07h dac1 lch volume oat1l7 oat1l6 oat 1l5 oat1l4 oat1l3 oat1l2 oat1l1 oat1l0 08h dac1 rch volume oat1r7 oat1r6 oat 1r5 oat1r4 oat1r3 oat 1r2 oat1r1 oat1r0 09h dac2 lch volume oat2l7 oat2l6 oat 2l5 oat2l4 oat2l3 oat2l2 oat2l1 oat2l0 0ah dac2 rch volume oat2r7 oat2r6 oat 2r5 oat2r4 oat2r3 oat 2r2 oat2r1 oat2r0 0bh headphone control 1 ptsa 0 hpz moff hpmtn pts2 pts1 pts0 0ch headphone control 2 0 0 0 hpga4 hpga3 hpga2 hpga1 hpga0 10h headphone control 3 0 0 amts2 amts1 amts0 0 0 0 note: data must not be written to the addresses from 0dh to 1fh. (except 10h) when the pdn pin = ?l?, the registers are initialized to their default values. when rstn bit = ?0?, the internal timing is reset, but registers are not initialized to their default values. the bits defined as 0 must contain a ?0? value.
[ak4685] ms1106-e-00 2009/08 - 43 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown pwhp pwda2 pwda1 pwad smda2 smda1 smad rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 1 0 0 0 1 rstn: internal timing reset 0: reset. control registers are not initialized. 1: normal operation (default) smad: adc digital soft mute enable 0: normal operation (default) 1: adc outputs soft-muted smda1: dac1 digital soft mute enable 0: normal operation (default) 1: all dac outputs soft-muted smda2: dac2 digital soft mute enable 0: normal operation (default) 1: all dac outputs soft-muted pwad: power-down control of adc 0: power-down 1: normal operation (default) pwda1: power-down control of dac1 0: power-down 1: normal operation (default) pwda2: power-down control of dac2 0: power-down 1: normal operation (default) pwhp: power-down control of headphone amplifier 0: power-down (default) 1: normal operation
[ak4685] ms1106-e-00 2009/08 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h analog mute 0 0 0 0 amt2rn amt2ln amt1rn amt1ln r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 amt1ln: analog soft mute control for dac1 lch. mt1ln pin amt1ln bit dac1lch analog mute status l 0 mute l 1 mute (default) h 0 mute (default) h 1 unmute table 23. dac1 lch analog mute control amt1rn: analog soft mute control for dac1 rch. mt1rn pin amt1rn bit dac1rch analog mute status l 0 mute l 1 mute (default) h 0 mute (default) h 1 unmute table 24. dac1 rch analog mute control amt2ln, amt2rn: analog soft mute control for dac2. mt2ln pin amt2ln bit amt2rn bit dac2 analog mute status l 0 0 mute (default) l 0 1 n/a l 1 0 n/a l 1 1 mute h 0 0 mute (default) h 0 1 n/a h 1 0 n/a h 1 1 unmute (n/a: not available) table 25. dac2 analog mute control
[ak4685] ms1106-e-00 2009/08 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h interface settings cksb1 cksb0 difc1 difc0 difb 0 difa1 difa0 r/w r/w r/w r/w r/w r/w rd r/w r/w default 0 0 1 1 1 0 1 1 difa1-0: audio format control for porta (default: i2s) difb: audio format control for portb (default: i2s) difc1-0: audio format control for portc (default: i2s) cksb1-0: adc clock control for master mode. (default: 256fs) addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h dac speed control 0 acks2 dfs21 dfs20 0 acks1 dfs11 dfs10 r/w rd r/w r/w r/w rd r/w r/w r/w default 0 0 0 0 0 0 0 0 dfs11-10: dac1 sampling speed control (default: normal speed mode) these settings are ignored in auto setting mode. acks1: dac1 auto setting mode 0: disable, manual setting mode (default) 1: enable, auto setting mode when acks1 bit = ?1?, the master clock frequency is detected automatically and the dfs11-10 bits are ignored. when acks1 bit = ?0?, dfs11-10 bits set the sampling speed mode. dfs21-20: dac2 sampling speed control (default: normal speed mode) these settings are ignored in auto setting mode. acks2: dac2 auto setting mode 0: disable, manual setting mode (default) 1: enable, auto setting mode when acks2 bit = ?1?, the master clock frequency is detected automatically and the dfs21-20 bits are ignored. when acks2 bit = ?0?, dfs21-20 bits set the sampling speed mode.
[ak4685] ms1106-e-00 2009/08 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h de-emphasis/ att speed dem21 dem20 dem11 dem10 0 0 atsad atsda r/w r/w r/w r/w r/w rd rd r/w r/w default 0 1 0 1 0 0 0 0 atsda: dac1/2 digital attenuator transition time control atsad: adc digital attenuator transition time control dem11-10: dac1 de-emphasis filter control dem21-20: dac2 de-emphasis filter control addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h adc lch volume iatl7 iatl6 iatl5 iatl4 iatl3 iatl2 iatl1 iatl0 06h adc rch volume iatr7 iatr6 i atr5 iatr4 iatr3 iatr2 iatr1 iatr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 1 0 0 0 0 iatl7-0, iatr7-0: adc volume level control (default: 0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h dac1 lch volume oat1l7 oat1l6 oat 1l5 oat1l4 oat1l3 oat1l2 oat1l1 oat1l0 08h dac1 rch volume oat1r7 oat1r6 oat 1r5 oat1r4 oat1r3 oat 1r2 oat1r1 oat1r0 09h dac2 lch volume oat2l7 oat2l6 oat 2l5 oat2l4 oat2l3 oat2l2 oat2l1 oat2l0 0ah dac2 rch volume oat2r7 oat2r6 oat 2r5 oat2r4 oat2r3 oat 2r2 oat2r1 oat2r0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 0 0 0 oat1l7-0, oat1r7-0, oat2l7-0, oat2r 7-0: dac1/2 volume level control (default: 0db)
[ak4685] ms1106-e-00 2009/08 - 47 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh headphone control 1 ptsa 0 hpz moff hpmtn pts2 pts1 pts0 r/w r/w rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 1 0 0 pts2-0: headphone-amp mute on/off transition time default: ?100?; typ. 16.4ms hpmtn: headphone-amp mute 0: mute (default) 1: normal output moff: soft transition for hpmtn bit change 0: enable (default) 1: disable hpz: headphone-amp pull-down control 0: ground mode (default) hpl/hpr pins are shorted to vss3. 1: hi-z mode hpl/hpr pins are pulled-down by 50k (typ) to vss5. ptsa: mute pin/bit transition time setting 0: fixed (pts2-0 = ?011?) (default) 1: controlled by pts2-0 bits addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch headphone control 2 0 0 0 hpga4 hpga3 hpga2 hpga1 hpga0 r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 1 1 0 0 1 hpga4-0: headphone-amp volume setting default: 19h; 0db refer table 19. addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h headphone control 3 0 0 amts2 amts1 amts0 0 0 0 r/w rd rd r/w r/w r/w rd rd rd default 0 0 0 0 0 0 0 0 amts2-0: analog mute clock source control default: ?000?; typ. 10.3ms refer table 22 .
[ak4685] ms1106-e-00 2009/08 - 48 - system design figure 28 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ak4685 diff to single circuit rvcom1 49 rin1+ 50 51 52 53 54 lin 1+ 55 lv c o m1 56 lrckb 57 bickb 58 sdtob2 59 sdtob1 60 mcko 61 tvdd 62 vss7 63 dvdd1 64 48 vco m lvcom 2 lin2+ lin2 - lampo2 rampo 2 rin2 - rin2+ rvcom2 vss 5 av dd 3 hp r hp l 1 xto 2 mcb/xti msb lrckc m c lk c bickc sd tic vss1 dvdd3 sda scl pd n mt1n mt2n dvdd2 vss2 vss4 32 pvdd 31 cn 30 cp 29 nc 28 lout - 27 lout+ 26 rout- 25 rout+ 24 vss3 23 avdd2 22 sgl 21 lrcka 20 mclka 19 bicka 18 sdtia 17 pvee 3 4 5 6 7 8 9 10 11 12 13 14 15 16 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10u 0.1u + + analog in1 rin1- rampo1 lampo1 lin 1- av dd1 vss6 3.3v d igital headphone 2. 2u audio dsp3 3.3v analog 2.2u 10u 0.1u mute circu it diff to single circuit mute circu it + 10u 0.1u audio dsp2 10u 0.1u + + 10u 0.1u + 10u 0.1u 10u + rf rf rf rf ri ri ri ri 6.8 6.8 rf rf ri ri rf rf ri ri 5v analog analog in2 5v analog audio dsp1 5v digital 10u 0.1u + 5v digita l 10u 0.1u + micro controller 5v digital 5v analog x ?tal c a nalog out figure 28. typical connection diagram (master mode) notes: - vss1-7 must be connected the same analog ground plane.
[ak4685] ms1106-e-00 2009/08 - 49 - 1. grounding and power supply decoupling the ak4685 requires careful attention to power supply and grounding arrangements. avdd1, avdd2, avdd3, dvdd1, dvdd2, dvdd3, tvdd and pvdd are usually supplied from analog supply in system. vss1-7 of the ak4685 must be connected to analog ground plane. system analog ground and digital ground must be connected separately near to where the supplies are brought onto the pr inted circuit board. decoupling capacitors should be as near to the ak4685 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference inputs the voltage of avdd1 sets the adc input range, avdd2(avdd3) sets the dac1(dac2) analog output range. normally, 0.1f ceramic capacitors should be connected be tween avdd1/2/3 pins and vss6/2/3 pins. the vcom pin is a signal ground of this chip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor attached between these vcom pins and vss6 pin eliminat es the effects of high frequency noise. no load current may be drawn from these vcom pins. all signals, especially clocks, should be kept away from the avdd1, avdd2, avdd3, and vcom pins in order to avoid unwanted coupling into the ak4685. 3. analog inputs the ak4685 receives the analog input through the single-ended pre-amp using extern al resistors. the input range is +/-3.3 x avdd1/5 vpp (typ. fs=48khz) at each analog input pins. each input pins are biased to 0v(typ) internally. the adc output data format is 2?s complement. the internal digital hpf removes the dc offset. the ak4685 samples the analog inputs at 64fs. the digital filte r rejects noise above the stop band except for multiples of 64fs. the ak4685 includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs. 4. analog outputs the dac1 outputs can be switched between single-ended and differential outputs. when differential output is selected, the output range is +/-2.56 x (avdd2)/5 vpp(typ). the input data format is two?s complement. the output voltage is positive full scale fo r 7fffffh (@24-bit) and negative full scale for 800000h (@24-bit). the ideal voltage is 0v for 000000h(@24-bit). th e internal switched-capacitor filter (scf) attenuates the noise generated by the delta-sigma modulator beyond the audio passband. when single-ended output is selected, the output range is+/-1.41 x (avdd2)/5 vpp(typ) centered around the vcom voltage. the internal switched-capacitor filter (scf) and con tinuous-time filter (ctf) attenua te the noise generated by the delta-sigma modulator beyond the audio passband. the dac2 outputs are single-ended output and it is for hea dphones. the output range is+/-1.71 x (avdd3)/5 vpp(typ) centered around the 0v.the input data format is two?s comp lement. the output voltage is positive full scale for 7fffffh (@24-bit) and negative full scale for 800000h (@24-bit). the ideal voltage is 0v for 000000h(@24-bit). the internal switched-capacitor filter (scf) and continuous-time filter (c tf) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. dc offsets on the analog outputs should be eliminated by ac coupling since the analog outputs have a dc offset. 5. attention to the pcb wiring analog input and output pins should be wired as short as po ssible in order to avoid unwanted coupling into the ak4685.
[ak4685] ms1106-e-00 2009/08 - 50 - package 64pin lqfp (unit: mm) material & lead finish package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatmen t: solder (pb free) plate 12.0 0.4 10.0 0.2 32 33 48 49 64 1 16 17 0.20 0.10 0.10 m 0.5 12.0 0.4 1.00 0.10 0.50 0.25 0 ~10 max 1.85 1.40 0.2 0.00~0.25 0.09~0.25
[ak4685] ms1106-e-00 2009/08 - 51 - marking 1 akm ak4685eq xxxxxxx 1) pin #1 indication 2) asahi kasei logo 3) marking code: ak4685eq 4) date code: xxxxxxx (7 digits) date (yy/mm/dd) revision reason page contents 09/08/18 00 first edition revision history
[ak4685] ms1106-e-00 2009/08 - 52 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or syst em is one designed or intended for lif e support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and a ll responsibility and liability fo r and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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